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AM28F256-120PC 参数 Datasheet PDF下载

AM28F256-120PC图片预览
型号: AM28F256-120PC
PDF下载: 下载PDF文件 查看货源
内容描述: 256千位(是32K ×8位)的CMOS 12.0伏,整体擦除闪存 [256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 35 页 / 467 K
品牌: AMD [ AMD ]
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FLASHERASE ELECTRICAL ERASE ALGORITHM  
This Flash memory device erases the entire array in  
parallel. The erase time depends on VPP, temperature,  
and number of erase/program cycles on the device. In  
general, reprogramming time increases as the number  
of erase/program cycles increases.  
algorithm. Erasure then continues with an initial erase  
operation. Erase verification (Data = FFh) begins at  
address 0000h and continues through the array to the  
last address, or until data other than FFh is  
encountered. If a byte fails to verify, the device is  
erased again. With each erase operation, an  
increasing number of bytes verify to the erased state.  
Typically, devices are erased in less than 100 pulses  
(one second). Erase efficiency may be improved by  
storing the address of the last byte that fails to verify in  
a register. Following the next erase operation,  
verification may start at the stored address location. A  
total of 1000 erase pulses are allowed per reprogram  
cycle, which corresponds to approximately 10 seconds  
of cumulative erase time. The entire sequence of erase  
and byte verification is performed with high voltage  
applied to the VPP pin. Figure 1 illustrates the electrical  
erase algorithm.  
The Flasherase electrical erase algorithm employs an  
interactive closed loop flow to simultaneously erase all  
bits in the array. Erasure begins with a read of the mem-  
ory contents. The device is erased when shipped from  
the factory. Reading FFh data from the device would  
immediately be followed by executing the Flashrite pro-  
gramming algorithm with the appropriate data pattern.  
Should the device be currently programmed, data other  
than FFh will be returned from address locations.  
Follow the Flasherase algorithm. Uniform and reliable  
erasure is ensured by first programming all bits in the  
device to their charged state (Data = 00h). This is  
accomplished using the Flashrite Programming  
Table 4. Flasherase Electrical Erase Algorithm  
Bus Operations  
Command  
Comments  
Entire memory must = 00h before erasure (Note 3)  
Note: Use Flashrite programming algorithm (Figure 3) for  
programming.  
Wait for V Ramp to V  
(Note 1)  
PP  
PPH  
Initialize:  
Addresses  
Standby  
PLSCNT (Pulse count)  
Erase Setup  
Erase  
Data = 20h  
Data = 20h  
Write  
Standby  
Duration of Erase Operation (t  
)
WHWH2  
Address = Byte to Verify  
Data = A0h  
Write  
Erase-Verify (Note 2)  
Stops Erase Operation  
Standby  
Read  
Write Recovery Time before Read = 6 µs  
Read byte to verify erasure  
Compare output to FFh  
Increment pulse count  
Standby  
Write  
Reset  
Data = FFh, reset the register for read operations  
Standby  
Wait for V Ramp to V  
(Note 1)  
PP  
PPL  
Notes:  
1. See AC and DC Characteristics for values of V parameters. The V power supply can be hard-wired to the device or  
PP  
PP  
switchable. When V is switched, V  
may be ground, no connect with a resistor tied to ground, or less than V + 2.0 V.  
PP  
PPL  
CC  
2. Erase Verify is performed only after chip erasure. A final read compare may be performed (optional) after the register is written  
with the read command.  
3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.  
Am28F256  
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