Interrupt Acknowledge Cycle Waveforms
t1
t2
t3
t4
tW
CLKOUTA
68
A19–A0
Address
7
8
S6
S6
S6
1
(b)
AD15–AD0*,
AD7–AD0**
2
12
Ptr
15
AO15–AO8**
Address
23
9
ALE
10
11
4
BHE*
BHE
31
21
INTA1–INTA0
DEN
20
(c)
19
3
22
22
DT/R
(d)
(a)
4
22
S2–S0
Status
Notes:
*
Am186ER microcontroller only
Am188ER microcontroller only
**
a The status bits become inactive in the state preceding t4.
b The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge
transition occurs prior to tCLDX (min).
c This parameter applies to an interrupt acknowledge cycle that follows a write cycle.
d If followed by a write cycle, this change occurs in the state preceding that write cycle.
Am186TMER and Am188TMER Microcontrollers Data Sheet
89
AMD [ AMD ]
