Switching Characteristics over Commercial Operating Ranges
Interrupt Acknowledge Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
40 MHz
Min
50 MHz
Min
No.
Symbol Description
Max
Max
Unit
General Timing Requirements
tDVCL
tCLDX
1
2
Data in Setup
Data in Hold
5
2
5
2
ns
ns
General Timing Responses
tCHSV
tCLSH
tCLDV
tCHDX
tCHLH
tLHLL
3
4
Status Active Delay
0
0
0
0
12
12
12
0
0
0
0
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Status Inactive Delay
Data Valid Delay
7
8
Status Hold Time
9
ALE Active Delay
12
12
12
10
12
10
tCLCL–5=20
10
11
12
15
19
20
21
22
23
31
68
Notes:
ALE Width
15
tCHLL
tAVLL
ALE Inactive Delay
AD Address Invalid to ALE Low(a)
AD Address Float Delay
DEN Inactive to DT/R Low(a)
Control Active Delay 1(b)
DEN Inactive Delay
Control Active Delay 2(c)
ALE High to Address Valid
Control Inactive Delay(b)
CLKOUTA High to A Address Valid
tCLCH
tCLCH
tCLAZ
tDXDL
tCVCTV
tCVDEX
tCHCTV
tLHAV
tCLAX=0
0
0
0
0
0
5
0
0
0
0
12
14
12
10
14
10
0
0
7.5
0
tCVCTX
tCHAV
12
10
10
10
0
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
b
c
Testing is performed with equal loading on referenced pins.
This parameter applies to the INTA1–INTA0 signals.
This parameter applies to the DEN and DT/R signals.
88
Am186TMER and Am188TMER Microcontrollers Data Sheet
AMD [ AMD ]
