P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating range
Interrupt Acknowledge Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
Description
General Timing Requirements
20 MHz
Min
25 MHz
Min
No. Symbol
Max
Max Unit
1
2
tDVCL Data in Setup
tCLDX Data in Hold
10
3
10
3
ns
ns
General Timing Responses
3
4
tCHSV Status Active Delay
0
0
0
0
25
25
25
0
0
0
0
20
20
20
ns
ns
ns
ns
ns
ns
ns
tCLSH Status Inactive Delay
tCLDV Data Valid Delay
tCHDX Status Hold Time
tCHLH ALE Active Delay
7
8
9
25
25
20
20
10
11
tLHLL
tCHLL
ALE Width
tCLCL–10=40
tCLCL–10=30
ALE Inactive Delay
AD Address Invalid to ALE
Low(a)
12
tAVLL
tCLCH
tCLCH
ns
15
19
20
21
22
23
31
tCLAZ AD Address Float Delay
tDXDL DEN Inactive to DT/R Low(a)
tCVCTV Control Active Delay 1(b)
tCVDEX DEN Inactive Delay
tCHCTV Control Active Delay 2(c)
tLHAV ALE High to Address Valid
tCVCTX Control Inactive Delay(b)
tCLAX=0
25
tCLAX=0
20
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
25
25
25
20
20
20
0
0
0
0
20
0
15
0
25
25
20
20
CLKOUTA High to A Address
68
tCHAV
Valid
0
0
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V.
a
b
c
Equal loading on referenced pins.
This parameter applies to the INTA1–INTA0 signals.
This parameter applies to the DEN and DT/R signals.
78
Am186/188EM and Am186/188EMLV Microcontrollers
AMD [ AMD ]
