P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating range
PSRAM Refresh Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
Description
20 MHz
Min
25 MHz
Min Max Unit
No. Symbol
General Timing Responses
Max
9
tCHLH ALE Active Delay
25
20
ns
ns
ns
tCLCL–10=
tCLCL–10=
30
10
tLHLL
ALE Width
40
11
tCHLL
ALE Inactive Delay
25
25
20
20
Read/Write Cycle Timing Responses
25
tCLRL
RD Active Delay
0
0
ns
ns
2tCLCL–15
=85
2tCLCL–15
=65
26
tRLRH RD Pulse Width
27
28
80
81
tCLRH RD Inactive Delay
tRHLH RD Inactive to ALE High(a)
tCLCLX LCS Inactive Delay
tCLCSL LCS Active Delay
0
25
0
20
ns
ns
ns
ns
tCLCH–3
tCLCH–3
0
0
25
25
0
0
20
20
Refresh Timing Cycle Parameters
79
82
85
86
tCLRFD CLKOUTA Low to RFSH Valid
tCLRF CLKOUTA High to RFSH Invalid
tRFCY RFSH Cycle Time
tLCRF
0
0
25
25
0
20
20
ns
ns
ns
0
6 • tCLCL
6 • tCLCL
2tCLCL–3
LCS Inactive to RFSH Active Delay 2tCLCL–3
Note:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V.
a
Equal loading on referenced pins.
Am186/188EM and Am186/188EMLV Microcontrollers
75
AMD [ AMD ]
