P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating range
PSRAM Refresh Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
Description
33 MHz
Min
40 MHz
Min Max Unit
No. Symbol
General Timing Responses
Max
9
tCHLH ALE Active Delay
15
12
ns
ns
ns
tCLCL–5
=20
10
tLHLL
ALE Width
tCLCL–10=20
11
tCHLL
ALE Inactive Delay
15
15
12
10
Read/Write Cycle Timing Responses
25
tCLRL
RD Active Delay
0
0
ns
ns
2tCLCL–15
=45
2tCLCL–10
=40
26
tRLRH RD Pulse Width
27
28
80
81
tCLRH RD Inactive Delay
tRHLH RD Inactive to ALE High(a)
tCLCLX LCS Inactive Delay
tCLCSL LCS Active Delay
0
15
0
12
ns
ns
ns
ns
tCLCH–3
tCLCH–2
0
0
15
15
0
0
12
12
Refresh Timing Cycle Parameters
79
82
85
86
tCLRFD CLKOUTA Low to RFSH Valid
tCLRF CLKOUTA High to RFSH Invalid
tRFCY RFSH Cycle Time
tLCRF LCS Inactive to RFSH Active Delay
0
15
15
0
0
12
12
ns
ns
ns
0
6 • tCLCL
2tCLCL –3
6 • tCLCL
2tCLCL –1.25
Note:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V.
a
Equal loading on referenced pins.
76
Am186/188EM and Am186/188EMLV Microcontrollers
AMD [ AMD ]
