P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating range
Software Halt Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
Description
General Timing Responses
20 MHz
Min
25 MHz
Min Max Unit
No. Symbol
Max
3
4
tCHSV Status Active Delay
tCLSH Status Inactive Delay
AD Address Invalid Delay and
BHE
tCHLH ALE Active Delay
0
0
25
25
0
0
20
20
ns
ns
5
tCLAV
0
25
25
0
20
20
ns
9
ns
ns
ns
ns
ns
10
11
19
22
tLHLL
ALE Width
tCLCL–10=40
tCLCL–10=30
tCHLL
ALE Inactive Delay
25
20
tDXDL DEN Inactive to DT/R Low(a)
tCHCTV Control Active Delay 2(b)
0
0
0
0
25
25
20
20
CLKOUTA High to A Address
Invalid
68
tCHAV
0
0
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V.
a
b
Equal loading on referenced pins.
This parameter applies to the DEN signal.
Am186/188EM and Am186/188EMLV Microcontrollers
81
AMD [ AMD ]
