P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating range
PSRAM Write Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
Description
General Timing Responses
33 MHz
Min
40 MHz
Min Max Unit
No. Symbol
Max
AD Address Valid Delay and
BHE
5
tCLAV
0
15
15
0
12
12
ns
7
tCLDV Data Valid Delay
tCHDX Status Hold Time
tCHLH ALE Active Delay
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
9
15
12
10
11
20
23
80
81
tLHLL
ALE Width
tCLCL–10=20
tCLCL–5=20
tCHLL
ALE Inactive Delay
15
15
12
12
tCVCTV Control Active Delay 1(b)
tLHAV ALE High to Address Valid
tCLCLX LCS Inactive Delay
tCLCSL LCS Active Delay
0
0
10
7.5
0
15
15
0
0
12
12
0
tCLCL + tCLCH
–3
tCLCL + tCLCH
–1.25
84
tLRLL
LCS Precharge Pulse Width
Write Cycle Timing Responses
30
31
tCLDOX Data Hold Time
tCVCTX Control Inactive Delay(b)
0
0
0
0
ns
ns
15
12
2tCLCL–10
=50
2tCLCL–10
=40
32
tWLWH WR Pulse Width
ns
33
34
tWHLH WR Inactive to ALE High(a)
tWHDX Data Hold after WR(a)
tCLCH–2
tCLCH–2
ns
ns
tCLCL–10=20
tCLCL–10=15
tCLCL+tCHCL
–3
tCLCL+tCHCL
–1.25
65
68
tAVWL A Address Valid to WR Low
ns
ns
ns
CLKOUTA High to A
tCHAV
0
15
15
0
10
12
Address Valid
A Address Valid to WHB,
WLB Low
87
tAVBL
tCHCL–3
tCHCL–1.25
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V.
a
b
Equal loading on referenced pins.
This parameter applies to the DEN, WR, WHB, and WLB signals.
Am186/188EM and Am186/188EMLV Microcontrollers
73
AMD [ AMD ]
