P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating range
PSRAM Read Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
Description
General Timing Requirements
20 MHz
Min
25 MHz
Min
No. Symbol
Max
Max Unit
1
2
tDVCL Data in Setup
tCLDX Data in Hold(b)
10
3
10
3
ns
ns
General Timing Responses
5
7
8
9
tCLAV AD Address Valid Delay and BHE
0
0
0
25
25
0
0
0
20
20
ns
ns
ns
ns
tCLDV Data Valid Delay
tCHDX Status Hold Time
tCHLH ALE Active Delay
25
20
tCLCL–10=
tCLCL–10=
30
10
tLHLL
ALE Width
ns
40
11
23
80
81
tCHLL
ALE Inactive Delay
25
20
ns
ns
ns
ns
tLHAV ALE High to Address Valid
tCLCLX LCS Inactive Delay
tCLCSL LCS Active Delay
20
0
15
0
25
25
20
20
0
0
tCLCL + tCLCH
–3
tCLCL + tCLCH
–3
84
tLRLL
LCS Precharge Pulse Width
ns
Read Cycle Timing Responses
24
25
tAZRL
tCLRL
AD Address Float to RD Active
RD Active Delay
0
0
0
0
ns
ns
25
25
20
20
2tCLCL–15
=85
2tCLCL–15
=65
26
tRLRH RD Pulse Width
ns
27
28
59
tCLRH RD Inactive Delay
0
tCLCH–3
0
0
tCLCH–3
0
ns
ns
ns
tRHLH RD Inactive to ALE High(a)
tRHDX RD High to Data Hold on AD Bus(b)
2tCLCL–15
=85
2tCLCL–15
=65
66
tAVRL A Address Valid to RD Low
ns
ns
68
tCHAV CLKOUTA High to A Address Valid
0
25
0
20
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V.
a
b
Equal loading on referenced pins.
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Am186/188EM and Am186/188EMLV Microcontrollers
69
AMD [ AMD ]
