Switching Characteristics over Commercial and Industrial Operating Ranges
Write Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
No. Symbol Description
General Timing Responses
25 MHz
Min
33 MHz
Min
Max
Max Unit
3
4
tCHSV Status Active Delay
0
0
0
0
0
20
20
20
20
0
0
0
0
0
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
tCLSH Status Inactive Delay
tCLAV AD Address Valid Delay
tCLDV Data Valid Delay
tCHDX Status Hold Time
tCHLH ALE Active Delay
tLHLL ALE Width
5
7
8
9
20
15
tCLCL–10=30
tCLCL–10=20
10
11
12
13
14
16
tCHLL ALE Inactive Delay
20
15
ns
ns
ns
ns
ns
tAVLL AD Address Valid to ALE Low(a)
tLLAX AD Address Hold from ALE Inactive(a)
tAVCH AD Address Valid to Clock High
tCLCSV MCS/PCS Active Delay
tCLCH
tCHCL
0
tCLCH
tCHCL
0
0
0
20
15
MCS/PCS Hold from Command
tCLCH
tCLCH
17
tCXCSX
ns
Inactive(a)
0
0
0
0
18
19
20
23
tCHCSX MCS/PCS Inactive Delay
tDXDL DEN Inactive to DT/R Low(a)
tCVCTV Control Active Delay 1(b)
tLHAV ALE High to Address Valid
20
20
15
15
ns
ns
ns
ns
0
0
15
10
Write Cycle Timing Responses
0
0
0
0
30
31
tCLDOX Data Hold Time
tCVCTX Control Inactive Delay(b)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
15
2tCLCL–10=70
tCLCH–2
tCLCL–10=30
tCLCH–3
tCLCL+tCHCL–3
0
2tCLCL–10=50
tCLCH–2
tCLCL–10=20
tCLCH–5
tCLCL+tCHCL–3
0
32
tWLWH WR Pulse Width
33
tWHLH WR Inactive to ALE High(a)
tWHDX Data Hold after WR(a)
34
35
tWHDEX WR Inactive to DEN Inactive(a)
tAVWL A Address Valid to WR Low
tCHCSV CLKOUTA High to LCS/UCS Valid
tCHAV CLKOUTA High to A Address Valid
tAVBL A Address Valid to WHB, WLB Low
65
67
20
20
20
15
15
15
0
0
68
tCHCL–3
tCHCL–3
87
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
b
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
Am186TMER and Am188TMER Microcontrollers Data Sheet
73
AMD [ AMD ]
