Switching Characteristics over Commercial and Industrial Operating Ranges
Internal RAM Show Read Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
25 MHz
Min
33 MHz
Min
No.
Symbol Description
Max
Max
Unit
General Timing Responses
tCLAV
tCLDV
tCHLH
tCHLL
5
7
AD Address Valid Delay
Data Valid Delay
0
0
20
20
20
20
0
0
15
15
15
15
ns
ns
ns
ns
9
ALE Active Delay
11
ALE Inactive Delay
Read Cycle Timing Responses
tCLRL
tCLRH
tCHAV
25
27
68
RD Active Delay
0
0
0
20
20
20
0
0
0
15
15
15
ns
ns
ns
RD Inactive Delay
CLKOUTA High to A Address Valid
Switching Characteristics over Commercial and Industrial Operating Ranges
Internal RAM Show Read Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
40 MHz
Min
50 MHz
Min
No.
Symbol Description
Max
Max
Unit
General Timing Responses
tCLAV
tCLDV
tCHLH
tCHLL
5
7
AD Address Valid Delay
Data Valid Delay
0
0
12
12
12
12
0
0
10
10
10
10
ns
ns
ns
ns
9
ALE Active Delay
11
ALE Inactive Delay
Read Cycle Timing Responses
tCLRL
tCLRH
tCHAV
25
27
68
RD Active Delay
0
0
0
10
12
10
0
0
0
10
10
10
ns
ns
ns
RD Inactive Delay
CLKOUTA High to A Address Valid
76
Am186TMER and Am188TMER Microcontrollers Data Sheet
AMD [ AMD ]
