Numerical Key to Switching Parameter Symbols
Parameter
Number Symbol Description
Parameter
Symbol
Number
43
Description
tCLCH
tCHCL
1
2
tDVCL
tCLDX
tCHSV
tCLSH
tCLAV
tCLAX
tCLDV
tCHDX
tCHLH
tLHLL
tCHLL
tAVLL
Data in Setup
CLKOUTA Low Time
CLKOUTA High Time
CLKOUTA Rise Time
CLKOUTA Fall Time
Data in Hold
44
tCH1CH2
tCL2CL1
tSRYCL
tCLSRY
tARYCH
tCLARX
tARYCHL
tARYLCL
tINVCH
tINVCL
3
Status Active Delay
Status Inactive Delay
AD Address Valid Delay
Address Hold
45
4
46
5
47
SRDY Transition Setup Time
SRDY Transition Hold Time
ARDY Resolution Transition Setup Time
ARDY Active Hold Time
ARDY Inactive Holding Time
ARDY Setup Time
6
48
7
Data Valid Delay
49
8
Status Hold Time
50
9
ALE Active Delay
51
10
11
12
13
14
15
16
ALE Width
52
ALE Inactive Delay
AD Address Valid to ALE Low
AD Address Hold from ALE Inactive
AD Address Valid to Clock High
AD Address Float Delay
MCS/PCS Active Delay
53
Peripheral Setup Time
DRQ Setup Time
54
tCLTMV
tRESIN
tHVCL
tLLAX
tAVCH
tCLAZ
tCLCSV
55
Timer Output Delay
57
RES Setup Time
58
HOLD Setup
tRHDX
59
RD High to Data Hold on AD Bus
MCS/PCS Hold from Command
Inactive
tLOCK
17
tCXCSX
61
Maximum PLL Lock Time
tCLHAV
tCHCZ
tCHCV
tAVWL
tAVRL
18
19
tCHCSX
tDXDL
tCVCTV
tCVDEX
tCHCTV
tLHAV
MCS/PCS Inactive Delay
DEN Inactive to DT/R Low
Control Active Delay 1
DEN Inactive Delay
Control Active Delay 2
ALE High to Address Valid
AD Address Float to RD Active
RD Active Delay
62
63
64
65
66
67
68
69
70
71
72
75
77
78
79
80
81
82
83
84
85
86
87
HLDA Valid Delay
Command Lines Float Delay
Command Lines Valid Delay (after Float)
A Address Valid to WR Low
A Address Valid to RD Low
CLKOUTA High to LCS/UCS Valid
CLKOUTA High to Address Valid
X1 to CLKOUTA Skew
20
21
22
tCHCSV
tCHAV
tCICOA
tCICOB
tCLEV
tCLSL
23
24
tAZRL
25
tCLRL
26
tRLRH
tCLRH
tRHLH
tRHAV
tCLDOX
tCVCTX
tWLWH
tWHLH
tWHDX
tWHDEX
tCKIN
RD Pulse Width
X1 to CLKOUTB Skew
27
RD Inactive Delay
CLKOUTA Low to SDEN Valid
CLKOUTA Low to SCLK Low
Data Valid to SCLK High
28
RD Inactive to ALE High
RD Inactive to AD address Active
Data Hold Time
tDVSH
tSHDX
tSLDV
29
30
SCLK High to SPI Data Hold
SCLK Low to SPI Data Valid
CLKOUTA High to RFSH Valid
LCS Inactive Delay
31
Control Inactive Delay
WR Pulse Width
tCHRFD
tCLCLX
tCLCSL
tCLRF
tCOAOB
tLRLL
32
33
WR Inactive to ALE High
Data Hold after WR
WR Inactive to DEN Inactive
X1 Period
34
LCS Active Delay
35
CLKOUTA High to RFSH Invalid
CLKOUTA to CLKOUTB Skew
LCS Precharge Pulse Width
RFSH Cycle Time
36
37
tCLCK
tCHCK
tCKHL
tCKLH
tCLCL
X1 Low Time
tRFCY
tLCRF
tAVBL
38
X1 High Time
39
X1 Fall Time
LCS Inactive to RFSH Active Delay
A Address Valid to WHB, WLB Low
40
X1 Rise Time
42
CLKOUTA Period
Notes:
The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76.
Am186TMER and Am188TMER Microcontrollers Data Sheet
69
AMD [ AMD ]
