Switching Characteristics over Commercial and Industrial Operating Ranges
Read Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
40 MHz
Min
50 MHz
Min
No.
Symbol Description
Max
Max Unit
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold(c)
5
2
5
2
ns
ns
General Timing Responses
3
4
tCHSV
tCLSH
tCLAV
tCLDV
tCHDX
tCHLH
tLHLL
Status Active Delay
Status Inactive Delay
AD Address Valid Delay
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
0
0
0
0
0
12
12
12
12
0
0
0
0
0
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
5
7
8
9
12
10
tCLCL–5=20
10
15
11
12
tCHLL
tAVLL
ALE Inactive Delay
AD Address Valid to ALE Low(a)
12
10
ns
ns
tCLCH
tCHCL
tCLCH
tCHCL
AD Address Hold from ALE
Inactive(a)
13
tLLAX
ns
0
tCLAX=0
0
0
0
0
14
15
16
tAVCH
tCLAZ
AD Address Valid to Clock High
AD Address Float Delay
MCS/PCS Active Delay
ns
ns
ns
12
12
10
10
tCLCSV
MCS/PCS Hold from Command
Inactive(a)
tCLCH
tCLCH
17
tCXCSX
ns
0
0
0
0
0
0
0
5
18
19
20
21
22
23
tCHCSX
tDXDL
MCS/PCS Inactive Delay
DEN Inactive to DT/R Low(a)
Control Active Delay 1(b)
DEN Inactive Delay
12
10
ns
ns
ns
ns
ns
ns
0
tCVCTV
tCVDEX
tCHCTV
tLHAV
12
14
12
10
14
10
0
Control Active Delay 2(b)
0
7.5
ALE High to Address Valid
Read Cycle Timing Responses
0
0
24
25
26
27
28
tAZRL
tCLRL
tRLRH
tCLRH
tRHLH
AD Address Float to RD Active
RD Active Delay
ns
ns
ns
ns
ns
0
2tCLCL–10=40
0
0
35
10
12
10
10
RD Pulse Width
0
RD Inactive Delay
RD Inactive to ALE High(a)
tCLCH–2
tCLCH–2
RD Inactive to AD Address
Active(a)
tCLCL–5=20
15
29
tRHAV
ns
0
0
59
66
tRHDX
tAVRL
tCHCSV
tCHAV
RD High to Data Hold on AD Bus(c)
ns
ns
ns
ns
2 • tCLCL–10=40
2 • tCLCL–10=30
A Address Valid to RD Low
0
0
0
0
67
CLKOUTA High to LCS/UCS Valid
CLKOUTA High to A Address Valid
12
10
10
10
68
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
b
c
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
If either specification 2 or specification 59 is met with respect to data hold time, the part will function correctly.
Am186TMER and Am188TMER Microcontrollers Data Sheet
71
AMD [ AMD ]
