P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Software Halt Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
Description
33 MHz
Min
40 MHz
Min
No. Symbol
General Timing Responses
Max
Max Unit
3
4
tCHSV
tCLSH
tCLAV
tCHLH
tLHLL
tCHLL
tDXDL
Status Active Delay
0
0
0
15
15
15
15
0
0
0
12
12
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
Status Inactive Delay
AD Address Invalid Delay and BHE
ALE Active Delay
5
9
10
11
19
22
68
ALE Width
tCLCL–10=20
tCLCL–5=20
ALE Inactive Delay
DEN Inactive to DT/R Low(a)
15
12
0
0
0
0
0
0
tCHCTV Control Active Delay 2(b)
15
15
12
10
tCHAV
CLKOUTA High to A Address
Invalid
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.45 V and VIH=2.4 V, except at X1 where VIH=VCC– 0.5 V.
a
b
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN signal.
Am186/188ES and Am186/188ESLV Microcontrollers
87
AMD [ AMD ]
