P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Interrupt Acknowledge Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
Description
General Timing Requirements
20 MHz
Min
25 MHz
Min
No. Symbol
Max
Max Unit
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
10
3
10
3
ns
ns
General Timing Responses
3
4
tCHSV
tCLSH
tCLDV
tCHDX
tCHLH
tLHLL
tCHLL
tAVLL
Status Active Delay
Status Inactive Delay
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
0
0
0
0
25
25
25
0
0
0
0
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
7
8
9
25
20
10
11
12
tCLCL–10=40
tCLCL–10=30
tCLCH
ALE Inactive Delay
25
20
AD Address Invalid to ALE
Low(a)
tCLCH
15
19
20
21
22
23
31
68
tCLAZ
tDXDL
AD Address Float Delay
DEN Inactive to DT/R Low(a)
tCLAX=0
25
tCLAX=0
20
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
tCVCTV Control Active Delay 1(b)
25
25
25
20
20
20
tCVDEX DEN Inactive Delay
tCHCTV Control Active Delay 2(c)
0
0
0
0
tLHAV
ALE High to Address Valid
20
0
15
0
tCVCTX Control Inactive Delay(b)
25
25
20
20
tCHAV
CLKOUTA High to A
Address Valid
0
0
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.45 V and VIH=2.4 V, except at X1 where VIH=VCC– 0.5 V.
a
b
Testing is performed with equal loading on referenced pins.
This parameter applies to the INTA1–INTA0 signals.
c
This parameter applies to the DEN and DT/R signals.
Am186/188ES and Am186/188ESLV Microcontrollers
83
AMD [ AMD ]
