P R E L I M I N A R Y
Interrupt Acknowledge Cycle Waveforms
t1
t2
t3
t4
tW
CLKOUTA
A19–A0
68
Address
7
8
S6/LOCK
S6
LOCK
S6
1
(b)
2
AD15–AD0*,
AD7–AD0**
12
15
Ptr
AO15–AO8**
Address
23
9
ALE
10
11
4
BHE*
BHE
31
21
INTA1–INTA0
DEN
20
(c)
19
3
22
22
DT/R
(d)
(a)
4
22
Status
S2–S0
Notes:
*
Am186ES microcontroller only
Am188ES microcontroller only
**
a
b
The status bits become inactive in the state preceding t4.
The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge
transition occurs prior to tCLDX (min).
c
This parameter applies for an interrupt acknowledge cycle that follows a write cycle.
If followed by a write cycle, this change occurs in the state preceding that write cycle.
d
Am186/188ES and Am186/188ESLV Microcontrollers
85
AMD [ AMD ]
