P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Clock (33 MHz and 40 MHz)
Preliminary
Parameter
Description
33 MHz
Min
40 MHz
Min
No. Symbol
CLKIN Requirements
Max
Max
Unit
36
37
38
39
40
tCKIN
tCLCK
tCHCK
tCKHL
tCKLH
X1 Period(a)
X1 Low Time (1.5 V)(a)
X1 High Time (1.5 V)(a)
X1 Fall Time (3.5 to 1.0 V)(a)
X1 Rise Time (1.0 to 3.5 V)(a)
30
10
10
60
25
7.5
7.5
60
ns
ns
ns
ns
ns
5
5
5
5
CLKOUT Timing
42
43
tCLCL
tCLCH
CLKOUTA Period
30
25
ns
CLKOUTA Low Time
(CL=50 pF)
0.5tCLCL–1.5
0.5tCLCL–1.25
=11.25
ns
=13.5
44
45
46
tCHCL
CLKOUTA High Time
(CL=50 pF)
0.5tCLCL–1.5
=13.5
0.5tCLCL–1.25
=11.25
ns
ns
ns
tCH1CH2 CLKOUTA Rise Time
(1.0 to 3.5 V)
3
3
3
3
tCL2CL1 CLKOUTA Fall Time
(3.5 to 1.0 V)
61
69
70
tLOCK
Maximum PLL Lock Time
1
1
ms
ns
ns
tCICOA X1 to CLKOUTA Skew
tCICOB X1 to CLKOUTB Skew
15
25
15
25
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.45 V and VIH=2.4 V, except at X1 where VIH=VCC– 0.5 V.
a
The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes.
The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2
mode should be used.
Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should
be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
90
Am186/188ES and Am186/188ESLV Microcontrollers
AMD [ AMD ]
