P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
PSRAM Refresh Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
Description
General Timing Responses
20 MHz
Min
25 MHz
Min
No. Symbol
Max
25
Max Unit
9
tCHLH
tLHLL
tCHLL
ALE Active Delay
ALE Width
20
20
20
20
ns
ns
ns
10
11
tCLCL–10=40
tCLCL–10=30
ALE Inactive Delay
25
Read/Write Cycle Timing Responses
25
26
27
28
80
81
tCLRL
tRLRH
tCLRH
tRHLH
RD Active Delay
0
25
0
ns
ns
ns
ns
ns
ns
RD Pulse Width
2tCLCL–15=85
2tCLCL–15=65
RD Inactive Delay
RD Inactive to ALE High(a)
0
25
0
tCLCH–3
tCLCH–3
tCLCLX LCS Inactive Delay
tCLCSL LCS Active Delay
0
0
25
25
0
0
20
20
Refresh Timing Cycle Parameters
79
82
85
86
tCLRFD CLKOUTA Low to RFSH Valid
0
25
25
0
20
20
ns
ns
ns
tCLRF
tRFCY
tLCRF
CLKOUTA High to RFSH Invalid
RFSH Cycle Time
0
0
6 • tCLCL
2tCLCL–3
6 • tCLCL
2tCLCL–3
LCS Inactive to RFSH Active
Delay
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.45 V and VIH=2.4 V, except at X1 where VIH=VCC– 0.5 V.
a
Testing is performed with equal loading on referenced pins.
80
Am186/188ES and Am186/188ESLV Microcontrollers
AMD [ AMD ]
