D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
Max
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (see Note)
tREADY
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (see Note)
tREADY
Max
500
ns
tRP
tRH
tRB
RESET# Pulse Width
Min
Min
Min
500
200
0
ns
ns
ns
RESET# High Time Before Read (see Note)
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14. RESET# Timings
36
Am29SL160C
21635C5 January 23, 2007