欢迎访问ic37.com |
会员登录 免费注册
发布采购

5962-9052701MXA 参数 Datasheet PDF下载

5962-9052701MXA图片预览
型号: 5962-9052701MXA
PDF下载: 下载PDF文件 查看货源
内容描述: TAXIchip集成电路(透明异步Xmitter ,接收器接口) [TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)]
分类和应用: 驱动器接口集成电路
文件页数/大小: 127 页 / 704 K
品牌: AMD [ AMD ]
 浏览型号5962-9052701MXA的Datasheet PDF文件第113页浏览型号5962-9052701MXA的Datasheet PDF文件第114页浏览型号5962-9052701MXA的Datasheet PDF文件第115页浏览型号5962-9052701MXA的Datasheet PDF文件第116页浏览型号5962-9052701MXA的Datasheet PDF文件第118页浏览型号5962-9052701MXA的Datasheet PDF文件第119页浏览型号5962-9052701MXA的Datasheet PDF文件第120页浏览型号5962-9052701MXA的Datasheet PDF文件第121页  
AMD  
active High, without any additional logic. The VLTN signal is used for both Command  
and Data violations. Buffering of the DSTRB and VLTN signals may be necessary as  
illustrated in Figure 15 to meet the drive requirements of the first column of registers.  
Da t a /Co m m a n d Ou t p u t No t e :  
In this system, when a nonSync Command byte is received the data line values  
corresponding to that byte will change to the values last output from the TAXI Receiver  
data lines. Conversely, when a data byte is received the command line values for that  
byte will change to the values last output from the TAXI Receiver command lines. This is  
a characteristic of the example given and depends on how the command and data  
information is latched.  
Alt e rin g t h e Nu m b e r o f Ou t p u t Byt e s :  
The above described design is an example of a four byte cascaded serial data receiving  
system. The same design techniques can be used to expand or reduce the number of  
bytes output at a time by the system. The considerations that should be taken into  
account for an altered system deal with board space and part cost in accordance with  
the requirements of the situation at hand. For board space note see the PAL Usage  
section below.  
P AL Us a g e :  
In this system, the use of a PAL could greatly reduce the amount of board space used.  
The PAL could incorporate all of the flip-flops and buffering logic as well as the first  
column of registers that capture the system information. The reason a PAL was not  
used in the system described above was to help ensure the understanding of the design  
concept. For this application it is recommended that the timing considerations men-  
tioned before should be investigated to ensure proper operation of the system.  
TAXIchip Integrated Circuits Technical Manual  
113  
 复制成功!