HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET
Parallel/Serial Conversion
The parallel-to-serial converter takes in 20-bit wide
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the transmit-
ter on the positive going edge of REFCLK. The data
is then clocked synchronous to the clock synthesis
unit serial clock into the serial output shift register.
The shift register is clocked by the internally gener-
ated bit clock which is 20 times the REFCLK input
frequency. The state of the serial outputs is controlled
by the output enable pins, OE0 and OE1. D[0] is
transmitted first.
Reference Clock Input
S8401/S8501
The reference clock input (REFCLK) must be supplied
with a PECL single-ended AC coupled crystal clock
source with 100 PPM tolerance to assure that the trans-
mitted data meets the SMPTE 292M Specification
frequency limits. The internal serial clock is frequency
locked to the reference clock. Refer to Table 1 for
reference clock frequency.
Table 1. Transmitter Operating Mode
Data Rate
(Mbps)
1485
Word
Width
(Bits)
20
Reference
Clock
Frequency
(MHz)
74.25
TCLK/TCLKN
Frequency
(MHz)
74.25
Figure 4. S8501 Functional Block Diagram
LOCKREFN
REFCLK
RX
RY
2:1
RLX
RLY
LPEN
D
LOCKDETN
SHIFT
REGISTER
PLL CLOCK
RECOVERY
BITCLK
D
Q
20
D[19:0]
RCLK
DIVIDER
RCLKN
December 10, 1999 / Revision C
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
