欢迎访问ic37.com |
会员登录 免费注册
发布采购

S8501QF 参数 Datasheet PDF下载

S8501QF图片预览
型号: S8501QF
PDF下载: 下载PDF文件 查看货源
内容描述: [Consumer Circuit, Bipolar, PQFP52, 10 X 10 MM, PLASTIC, QFP-52]
分类和应用: 商用集成电路
文件页数/大小: 18 页 / 146 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号S8501QF的Datasheet PDF文件第2页浏览型号S8501QF的Datasheet PDF文件第3页浏览型号S8501QF的Datasheet PDF文件第4页浏览型号S8501QF的Datasheet PDF文件第5页浏览型号S8501QF的Datasheet PDF文件第6页浏览型号S8501QF的Datasheet PDF文件第7页浏览型号S8501QF的Datasheet PDF文件第8页浏览型号S8501QF的Datasheet PDF文件第9页  
®
DEVICE
SPECIFICATION
HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET
HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET
BiCMOS PECL CLOCK GENERATOR
GENERAL DESCRIPTION
S8401/S8501
S8401/S8501
FEATURES
Micro-Power Bipolor technology
SMPTE 292M compliant
1.485 Gb/s or 1.485/1.001 Gb/s operation
HD-SDI Serializer transmitter incorporates a
Phase Lock Loop (PLL) providing clock synthe-
sis from low-speed reference
HD-SDI Deserializer receiver PLL configured
for clock and data recovery
20-bit parallel TTL compatible interface
Low-jitter serial PECL compatible interface
Lock detect
Local loopback
Continuous downstream clocking from receiver
Single +3.3V power supply
Compact 52 PQFP package
The S8401 and S8501 transmitter and receiver pair
are designed to perform HD-SDI over fiber optic or
coaxial cable interfaces conforming to the require-
ments of the SMPTE 292M. The chipset supports
1.485 Gb/s with an associated 20-bit data word.
The chipset performs parallel-to-serial and serial-to-
parallel conversion for scrambled data. The S8401
on-chip PLL synthesizes the high-speed clock from a
low-speed reference. The S8501 on-chip PLL syn-
chronizes directly to incoming digital signals, to receive
the data stream. The transmitter and receiver each
support differential PECL I/O for fiber optic compo-
nent interfaces, to minimize crosstalk and maximize
data integrity. Local loopback allows for system diag-
nostics.
The S8401 and S8501 operate from +3.3V power
supplies. Each chip typically dissipates only 0.70 and
0.90W respectively. Figure 1 shows a typical network
configuration incorporating the chipset.
APPLICATIONS
Parallel to HD-SDI/HD-SDI to parallel interfacing
• Compressors
• Video graphics
• Video editors
• Disc storage devices
• VTR’s
• Cameras
• Monitors
• Frame synchronizers
• Character generators
Figure 1. System Block Diagram
Coax
or
Fibre
FPGA
Scrambler
20
S8401
HD-SDI
Serializer
DRV
EQ
S8501
20
HD-SDI
Deserializer
FPGA
Descrambler
Framer
December 10, 1999 / Revision C
1