S8401/S8501
HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET
Loopback
Local loopback is supported by the chipset, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
S8401/S8501 OVERVIEW
The S8401 transmitter and S8501 receiver provide
serialization and deserialization functions for
scrambled data to implement a HD-SDI. Operation of
the S8401/S8501 chips is straightforward, as depicted
in Figure 2. The sequence of operations is as follows:
Transmitter
1. 20-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. 20-bit parallel output
The 20-bit parallel data handled by the S8401 and
S8501 devices should be from a DC-balanced en-
coding scheme, such as the scrambling as defined
by SMPTE-292M.
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 5.
A lock detect feature is provided on the receiver, which
indicates that the PLL is locked (synchronized) to the
data stream.
Figure 2. Interface Diagram
20 Bit
Parallel
Data In
TCLK
Transmitter
S8401
Loopback
REFCLK
REFCLK
Loopback
Serial
Data
Receiver
S8501
Parallel
Data Out
RCLK
RCLKN
Lock
Detect
S8401 TRANSMITTER
Architecture/Functional Description
The S8401 transmitter accepts parallel input data and
serializes it for transmission over fiber optic or coaxial
cable media. The S8401 is compliant with SMPTE
292M Specification, and supports the HD-SDI data
rate of 1.485 Gb/s.
The parallel input data word is 20 bits wide. A block
diagram showing the basic chip function is shown in
Figure 3.
Figure 3. S8401 Functional Block Diagram
OE0
OE1
10
20
10
D
Q
10
D[19:0]
2:1
TX
TY
TEST
CONTROL
LOGIC
SHIFT
REGISTER
TLX
TLY
DIVIDE-BY-20
REFCLK
PLL CLOCK
MULTIPLIER
F0 = F1 X 20
TCLK
TCLKN
2
December 10, 1999 / Revision C