S8401/S8501
HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET
Table 5. S8501 Pin Assignment and Descriptions
Pin Name
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LOCKDETN
Level
TTL
I/O
O
Pin #
45
43
42
40
38
37
35
34
32
31
29
28
25
24
22
21
18
17
15
14
52
Description
Outputs parallel data. Parallel data on this bus is clocked out on
the falling edge of RCLK. D[0] is the first bit received.
TTL
O
Lock Detect. When Low, LOCKDETN indicates that the PLL is
locked to the incoming data stream. When High, it provides a
system flag indicating that the PLL is locked to the local
reference clock.
Loop Enable. Active High. When active, LPEN selects the
loopback serial input pins RLX and RLY. When inactive, LPEN
selects the received serial data input pins RX and RY (normal
operation).
Receive Clock. Parallel data is clocked out on the falling edge of
RCLK.
Reference Clock. (Externally capacitively coupled.) A free-
running crystal-controlled reference clock for the PLL clock
multiplier. The frequency of REFCLK is shown in Table 2.
Receive Loopback Serial Inputs. (Externally capacitively
coupled.) The serial loopback data inputs. RLX is the positive
input, and RLY is the negative input. See Figure 16 if not used.
Receive Serial Inputs. (Externally capacitively coupled.) The
received serial data inputs. RX is the positive input, and RY is
the negative input. See Figure 16 if not used.
LPEN
TTL
I
8
RCLK
RCLKN
REFCLK
Diff.
TTL
LVPECL
O
I
49
48
2
RLX
RLY
RX
RY
Diff.
PECL
Diff.
PECL
I
11
12
9
10
I
8
December 10, 1999 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
