Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
The master read transfer count register is used to con-
vey to the PCI controller the actual number of bytes
that are to be transferred. The value in this register is
decremented with each bus master PCI read opera-
tion until the transfer count reaches zero. Upon
reaching zero, the transfer operation ceases and an
interrupt may be optionally generated to either the PCI
or Add-On bus interface. Transfers which are not
whole multiples of DWORDs in size result in a partial
word ending cycle. This partial word ending cycle is
possible since all bus master transfers for this control-
ler are required to begin on a DWORD boundary.
PCI CONTROLLED BUS MASTER READ
TRANSFER COUNT REGISTER (MRTC)
Master Read Transfer Count
Register Name
PCI Address Offset
Power-up value
Attribute
30h
00000000h
Read/Write
32 bits
Size
Under certain circumstances, MRTC can be accessed
from the Add-On bus instead of the PCI bus.
Figure 27. PCI Controlled Bus Master Read Transfer Count Register
31
26 25
0
Bit
00
Value
Transfer Count
in Bytes (R/W)
Reserved = 0's (RO)
AMCC Confidential and Proprietary
DS1527
65
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
