Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
OUTGOING MAILBOX REGISTERS (OMB)
These four DWORD registers provide a method for sending command or
parameter data to the Add-On system. PCI bus operations to these regis-
ters may be in any width (byte, word, or DWORD). Writing to these regis-
ters can be a source for Add-On bus interrupts (if desired) by enabling
their interrupt generation through the use of the Add-On’s interrupt con-
trol/status register.
Outgoing Mailboxes 1-4
00h, 04h, 08h, 0Ch
XXXXXXXXh
Register Names
PCI Address Offset
Power-up value
Attribute
Read/Write
32 bits
Size
INCOMING MAILBOX REGISTERS (IMB)
These four DWORD registers provide a method for receiving user defined
Incoming Mailboxes 1-4
10h, 14h, 18h, 1Ch
XXXXXXXXh
Register Names
PCI Address Offset
Power-up value
Attribute
data from the Add-On system. PCI bus read operations to these registers
may be in any width (byte, word, or DWORD). Only read operations are
supported. Reading from these registers can optionally cause an Add-On
bus interrupt (if desired) by enabling their interrupt generation through the
use of the Add-On’s interrupt control/status register. Mailbox 4, byte 3 only
exists as device pins on the S5935 devices when used with a serial non-
volatile memory.
Read Only
32 bits
Size
FIFO REGISTER PORT (FIFO)
This location provides access to the bidirectional FIFO. Separate registers
are used when reading from or writing to the FIFO. Accordingly, it is not
possible to read what was written to this location. The FIFO registers are
implicitly involved in all bus master operations and, as such, should not be
accessed during active bus master transfers. When operating upon the
FIFOs with software program transfers involving word or byte operations,
the endian sequence of the FIFO should be established as described
under FIFO Endian Conversion Management in order to preserve the
internal FIFO data ordering and flag management. The FIFO’s fullness
may be observed by reading the master control-status register or MCSR
register.
FIFO Port
20h
Register Name
PCI Address Offset
Power-up value
Attribute
XXXXXXXXh
Read/Write
32 bits
Size
AMCC Confidential and Proprietary
DS1527
61
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
