Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
This register provides empty/full visibility of each byte
within the mailboxes. The empty/full status for the Out-
going mailboxes is displayed on the low-order 16 bits
and the empty/full status for the Incoming mailboxes is
presented on the high-order 16 bits. A value of 1 signi-
fies that a given mailbox has been written by one bus
interface but has not yet been read by the correspond-
ing destination interface. A PCI bus incoming mailbox
is defined as one in which data travels from the Add-
On bus into the PCI bus, and an outgoing mailbox is
defined as one where data travels out from the PCI
bus to the Add-On interface.
MAILBOX EMPTY FULL/STATUS REGIS-
TER (MBEF)
Mailbox Empty/Full Status
Register Name
PCI Address Offset
Power-up value
Attribute
34h
00000000h
Read Only
32 bits
Size
Figure 28. Mailbox Empty/Full Status Register
31
16 15
0
Bit
Value
Outgoing Mailbox
Status (RO)
Incoming Mailbox
Status (RO)
66
DS1527
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
