Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
PCI BUS INTERRUPTS ...................................................................................................................................... 114
PCI BUS PARITY ERRORS ................................................................................................................................ 114
ADD-ON BUS INTERFACE ................................................................................................................................. 116
ADD-ON OPERATION REGISTER ACCESSES ................................................................................................ 116
Add-On Interface Signals .............................................................................................................................. 116
System Signals .............................................................................................................................................. 116
Register Access Signals ................................................................................................................................ 116
Asynchronous Register Accesses ................................................................................................................. 117
Synchronous FIFO and Pass-Thru Data Register Accesses ........................................................................ 117
nv Memory Accesses Through the Add-On General Control/Status Register ............................................... 117
MAILBOX BUS INTERFACE .............................................................................................................................. 117
Mailbox Interrupts .......................................................................................................................................... 120
FIFO BUS INTERFACE ....................................................................................................................................... 120
FIFO Direct Access Inputs ............................................................................................................................. 120
FIFO Status Signals ...................................................................................................................................... 120
FIFO Control Signals ..................................................................................................................................... 120
PASS-THRU BUS INTERFACE .......................................................................................................................... 120
Pass-Thru Status Indicators .......................................................................................................................... 120
Pass-Thru Control Inputs ............................................................................................................................... 120
NON-VOLATILE MEMORY INTERFACE ........................................................................................................... 121
Non-Volatile Memory Interface Signals ......................................................................................................... 121
Accessing Non-Volatile Memory .................................................................................................................... 121
nv Memory Device Timing Requirements ...................................................................................................... 124
MAILBOX OVERVIEW ........................................................................................................................................ 126
FUNCTIONAL DESCRIPTION ............................................................................................................................ 126
Mailbox Empty/Full Conditions ...................................................................................................................... 127
Mailbox Interrupts .......................................................................................................................................... 127
Add-On Outgoing Mailbox 4, Byte 3 Access ................................................................................................. 127
BUS INTERFACE ................................................................................................................................................ 128
PCI Bus Interface .......................................................................................................................................... 128
Add-On Bus Interface .................................................................................................................................... 128
8-Bit and 16-Bit Add-On Interfaces ................................................................................................................ 128
CONFIGURATION ............................................................................................................................................... 129
Mailbox Status ............................................................................................................................................... 129
Mailbox Interrupts .......................................................................................................................................... 130
FIFO OVERVIEW ................................................................................................................................................ 134
FUNCTIONAL DESCRIPTION ............................................................................................................................ 134
FIFO Buffer Management and Endian Conversion ....................................................................................... 134
FIFO Advance Conditions ............................................................................................................................. 134
Endian Conversion ........................................................................................................................................ 135
64-Bit Endian Conversion .............................................................................................................................. 136
Add-On FIFO Status Indicators ..................................................................................................................... 137
Add-On FIFO Control Signals ........................................................................................................................ 137
PCI Bus Mastering with the FIFO .................................................................................................................. 137
Add-On Initiated Bus Mastering ..................................................................................................................... 137
6
DS1527
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
