Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
Figure 41. Serial Interface Byte Access — Write ................................................................................................... 94
Figure 42. Serial Interface Byte Access — Read ................................................................................................... 94
Figure 43. PCI AD Bus Definition During a Type 0 Configuration Access ............................................................. 95
Figure 44. Type 0 Configuration Read Cycles ....................................................................................................... 96
Figure 45. Type 0 Configuration Write Cycles ....................................................................................................... 96
Figure 46. Zero Wait State Burst Read PCI Bus Transfer (S5935 as Initiator) .................................................... 102
Figure 47. Single Data Phase PCI Bus Read of S5935 Registers (S5935 as Target) ......................................... 103
Figure 48. Burst PCI Bus Read Attempt to S5935 Registers (S5935 as Target) ................................................. 103
Figure 49. Zero Wait State Burst Write PCI Bus Transfer (S5935 as Initiator) .................................................... 104
Figure 50. Single Data Phase PCI Bus Write of S5935 Registers (S5935 as Target) ......................................... 105
Figure 51. Master-Initiated, Normal Completion (S5935 as either Target or Initiator) ......................................... 105
Figure 52. Master Initiated Termination Due to Preemption and Latency Timer Active (S5935 as Master) ........ 106
Figure 53. Master Initiated Termination Due to Preemption and Latency Timer Expired (S5935 as Master) ...... 106
Figure 54. Master Abort, No Response ............................................................................................................... 107
Figure 55. Target Disconnect Example 1 (IRDY# deasserted) ............................................................................ 108
Figure 56. Target-Initiated Retry .......................................................................................................................... 109
Figure 57. Target Abort Example ......................................................................................................................... 110
Figure 58. PCI Bus Arbitration and S5935 Bus Ownership Example ................................................................... 110
Figure 59. PCI Bus Access Latency Components ............................................................................................... 111
Figure 60. Engaging the LOCK# Signal ............................................................................................................... 112
Figure 61. Access to a Locked Target by its Owner ............................................................................................ 113
Figure 62. Access Attempt to a Locked Target .................................................................................................... 113
Figure 63. Error Reporting Signals ...................................................................................................................... 115
Figure 64. Asynchronous Add-On Operation Register Read ............................................................................... 118
Figure 65. Asynchronous Add-On Operation Register Write ............................................................................... 118
Figure 66. Synchronous FIFO or Pass-Thru Data Register Read ....................................................................... 119
Figure 67. Synchronous FIFO or Pass-Thru Data Register Write ........................................................................ 119
Figure 68. nv Memory Read Operation ................................................................................................................ 124
Figure 69. nv Memory Write Operation ................................................................................................................ 125
Figure 70. Block Diagram - PCI to Add-On Mailbox Register .............................................................................. 126
Figure 71. Block Diagram - Add-On to PCI Mailbox Register .............................................................................. 126
Figure 72. INTCSR FIFO Advance and Endian Control Bits ................................................................................ 134
Figure 73. Figure 2a. 16-bit Endian Conversion .................................................................................................. 135
Figure 74. PCI Read from a Full S5935 FIFO ...................................................................................................... 140
Figure 75. PCI Read from an Empty S5935 FIFO (Target Disconnect) ............................................................... 140
Figure 76. PCI Write to an Empty S5935 FIFO .................................................................................................... 141
Figure 77. PCI Write to a Full S5935 FIFO (Target Disconnect) .......................................................................... 141
Figure 78. Synchronous FIFO Register Burst Read Access Example ................................................................. 143
Figure 79. Synchronous FIFO Register Burst RDFIFO# Access Example .......................................................... 144
Figure 80. Single Cycle Pass-Thru Write ............................................................................................................. 153
Figure 81. Single Cycle Pass-Thru Write with PTADR# ...................................................................................... 154
10
DS1527
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
