Minimum Grant Register (MINGNT) ................................................................................................... 3-42
Maximum Latency Register (MAXLAT) ............................................................................................... 3-43
Outgoing Mailbox Registers (OMB) ....................................................................................................
Incoming Mailbox Registers (IMB) ......................................................................................................
FIFO Register Port (FIFO) ..................................................................................................................
PCI Controlled Bus Master Write Address Register (MWAR) .............................................................
PCI Controlled Bus Master Write Transfer Count Register (MWTC) ..................................................
PCI Controlled Bus Master Read Address Register (MRAR) .............................................................
PCI Controlled Bus Master Read Transfer Count Register (MRTC) ...................................................
Mailbox Empty Full/Status Register (MBEF) .......................................................................................
Interrupt Control/Status Register (INTCSR) ........................................................................................
Master Control/Status Register (MCSR) .............................................................................................
Add-On Incoming Mailbox Registers (AIMBx) ....................................................................................
Add-On Outgoing Mailbox Registers (AOMBx) ...................................................................................
Add-On FIFO Register Port (AFIFO) ..................................................................................................
Add-On Controlled Bus Master Write Address Register (MWAR) .......................................................
Add-On Pass-Thru Address Register (APTA) .....................................................................................
Add-On Pass-Thru Data Register (APTD) ..........................................................................................
Add-On Controlled Bus Master Read Address Register (MRAR) .......................................................
Add-On Empty/Full Status Register (AMBEF) ....................................................................................
Add-On Interrupt Control/Status Register (AINT) ...............................................................................
Add-On General Control/Status Register (AGCSTS) .........................................................................
Add-On Controlled Bus Master Write Transfer Count Register (MWTC) ............................................
Add-On Controlled Bus Master Read Transfer Count Register (MRTC) ............................................
PCI Reset ............................................................................................................................................
Loading From Byte-wide nv Memories ...............................................................................................
Loading From Serial nv Memories ......................................................................................................
PCI Bus Configuration Cycles .............................................................................................................
Expansion BIOS ROMs ......................................................................................................................
PCI Bus Transactions .........................................................................................................................
PCI Burst Transfers .................................................................................................................
PCI Read Transfers .................................................................................................................
PCI Write Transfers .................................................................................................................
Master-Initiated Termination ....................................................................................................
Normal Cycle Completion ........................................................................................................
Initiator Preemption .................................................................................................................
Master Abort ............................................................................................................................
Target-Initiated Termination .....................................................................................................
ii
4-46
4-46
4-46
4-47
4-48
4-49
4-50
4-51
4-53
4-57
5-62
5-62
5-62
5-63
5-64
5-64
5-65
5-66
5-68
5-71
5-74
5-75
6-77
6-77
6-78
6-80
6-82
7-86
7-86
7-88
7-89
7-89
7-89
7-90
7-91
7-91
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
