®
PCI BUS INTERFACE
S5935
PCI BUS INTERFACE
data phase consists of at least one PCI clock. FRAME#
is deasserted to indicate that the final data phase of a
PCI cycle is occurring. Wait states may be added to any
data phase (each wait state is one PCI clock).
This section describes the various events which oc-
cur on the S5935 PCI bus interface. Since the S5935
controller functions as both a target (slave) and an
initiator (master), signal timing detail is given for both
situations this Section presents the signal relation-
ships involved in performing basic read or write trans-
fers on the PCI bus and also describes the different
ways these cycles may complete.
The PCI bus command presented on the C/BE[3:0]#
pins during the address phase can represent 16 pos-
sible states. Table 1 lists the PCI commands and identi-
fies those which are supported by the S5935 controller
as a target and those which may be produced by the
S5935 controller as an initiator. A “Yes” in the “Sup-
ported As Target” column in Table 1 indicates the
S5935 controller asserts the signal DEVSEL# when that
command is issued along with the appropriate PCI ad-
dress. Two commands are supported by the S5935
controller as an initiator: Memory Read and Memory
Write.
PCI BUS TRANSACTIONS
Because the PCI bus has multiplexed address/data
pins, AD[31:0], each PCI bus transaction consists of
two phases: Address and Data. An address phase is
defined by the clock period when the signal FRAME#
transitions from inactive (high) to active (low). During
the address phase, a bus command is also driven by
the initiator on signal pins C/BE[3:0]#. If the command
indicates a PCI read, the clock cycle following the ad-
dress phase is used to perform a “bus turn-around”
cycle. A turn-around cycle is a clock period in which the
AD bus is not driven by the initiator or the target device.
This is used to avoid PCI bus contention. For a write
command, a turn-around cycle is not needed, and the bus
goes directly from the address phase to the data phase.
The completion or termination of a PCI cycle can be
signaled in several ways. In most cases, the comple-
tion of the final data phase is indicated by the asser-
tion of ready signals from both the target (TRDY#)
and initiator (IRDY#) while FRAME# is inactive. In
some cases, the target is not be able to continue or
support a burst transfer and asserts the STOP# sig-
nal. This is referred to as a target disconnect. There
are also cases where an addressed device does not
exist, and the signal DEVSEL# never becomes ac-
tive. When no DEVSEL# is asserted in response to a
PCI cycle, the initiator is responsible for ending the
cycle. This is referred to as a master abort. The bus
is returned to the idle phase when both FRAME# and
IRDY# are deasserted.
All PCI bus transactions consist of an address phase
(described above), followed by one or more data
phases. The address phase is only one PCI clock long
and the bus cycle information (address and command)
is latched internally by the S5935. The number of data
phases depends on how many data transfers are de-
sired or are possible with a given initiator-target pair. A
Table 1. Supported PCI Bus Commands
Supported
As Target
Supported
As Initiator
C/BE[3:0]#
Command Type
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
No
No
Yes
Yes
No
No
No
No
No
No
No
Yes
Yes
No
No
No
No
No 3
No
No
No
Reserved
No
Memory Read
Memory Write
Reserved
Yes
Yes
No
Reserved
No
Configuration Read
Configuration Write
Memory Read Multiple
Reserved
Memory Read Line
Memory Write & Invalidate
Yes
Yes
Yes 1
No
Yes 1
Yes 2
1. Memory Read Multiple and Read Line are treated as Memory Reads.
2. Memory Write & Invalidate commands are treated as Memory Writes.
3. Must be enabled by bit 15 MCSR.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
