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PCI BUS OPERATION REGISTERS
S5935
PCI BUS OPERATION REGISTERS
The PCI bus operation registers are mapped as 16 consecutive DWORD registers located at the address space
(I/O or memory) specified by the Base Address Register 0. These locations are the primary method of communi-
cation between the PCI and Add-On buses. Data, software-defined commands and command parameters can be
either exchanged through the mailboxes, transferred through the FIFO in blocks under program control, or
transferred using the FIFOs under Bus Master control. Table 1 lists the PCI Bus Operation Registers.
Table 1. Operation Registers — PCI Bus
Address Offset
Abbreviation
Register Name
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
OMB1
OMB2
OMB3
OMB4
IMB1
Outgoing Mailbox Register 1
Outgoing Mailbox Register 2
Outgoing Mailbox Register 3
Outgoing Mailbox Register 4
Incoming Mailbox Register 1
Incoming Mailbox Register 2
Incoming Mailbox Register 3
Incoming Mailbox Register 4
FIFO Register port (bidirectional)
Master Write Address Register
Master Write Transfer Count Register
Master Read Address Register
Master Read Transfer Count Register
Mailbox Empty/Full Status
IMB2
IMB3
IMB4
FIFO
MWAR
MWTC
MRAR
MRTC
MBEF
INTCSR
MCSR
Interrupt Control/Status Register
Bus Master Control/Status Register
4-45
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
