DEVICE SPECIFICATION
PCI CONTROLLER
3.3.2 FIFO Access Pins
S5933
Signal
Type
Description
WRFIFO#
in
Write FIFO. This signal provides a method to directly write the FIFO without having to
generate the SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO.
Access width is either 32 bits or 16 bits depending on the data bus size available.
This signal is intended for implementing PCI DMA transfers with the Add-On system.
This pin has an internal pull-up resistor.
RDFIFO#
in
Read FIFO. This signal provides a method to directly read the FIFO without having to
generate the SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO.
Access width is either 32 bits or 16 bits, depending on the data bus size defined by
the MODE pin. This signal is intended for implementing PCI DMA transfers with the
Add-On system. This pin has an internal pull-up resistor.
WRFULL
out
out
Write FIFO full. This pin indicates whether the Add-On-to-PCI bus FIFO is able to
accept more data. This pin is intended to be used to implement DMA hardware on
the Add-On system bus. A logic low output from this pin can be used to represent a
DMA write (Add-On to-PCI FIFO) request.
RDEMPTY
Read FIFO Empty. This pin indicates whether the read FIFO (PCI-to-Add-On FIFO)
contains data. This pin is intended to be used by the Add-On system to control DMA
transfers from the PCI bus to the Add-On system bus. A logic low from this pin can
be used to represent a DMA (PCI-to-Add-On FIFO) request.
3.3.3 Pass-Thru Interface Pins
Signal
Type
Description
PTATN#
out
Pass-Thru Attention. This signal identifies that an active PCI bus cycle has been
decoded and data must be read from or written to the Pass-Thru Data Register.
PTBURST#
PTRDY#
out
in
Pass-Thru Burst. This signal identifies PCI bus operations involving the current Pass-
Thru cycle as requesting burst access.
Pass-Thru Ready. This input indicates when Add-On logic has completed a Pass-
Thru cycle and another may be initiated.
PTNUM[1:0]
out
Pass-Thru Number. These signals identify which of the four base address registers
decoded a Pass-Thru bus activity. These bits are only meaningful when signal
PTATN# is active. A value of 00 corresponds to Base Address Register 1, a value of
01 for Base Address Register 2, and so on.
PTBE[3:0]#
PTADR#
out
in
Pass-Thru Byte Enables. These signals indicate which bytes are requested for a given
Pass-Thru operation. They are valid during the presence of signal PTATN# active.
Pass-Thru Address. This signal causes the actual Pass-Thru requested address to
be presented as outputs on the DQ pins DQ[31:0] for Add-Ons with 32-bit buses, or
the low-order 16 bits for Add-Ons with 16-bit buses. It is necessary that all other bus
control signals be in their inactive state during the assertion of PTADR#. The purpose
of this signal is to provide the direct addressing of external Add-On peripherals
through use of the PTNUM[1:0] and the low-order address bits presented on the DQ
bus with this pin active.
PTWR
out
Pass-Thru Write. This signal identifies whether a Pass-Thru operation is a read or
write cycle. This signal is valid only when PTATN# is active.
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