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S5933Q/7C 参数 Datasheet PDF下载

S5933Q/7C图片预览
型号: S5933Q/7C
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PQFP160, PLASTIC, QFP-160]
分类和应用: 时钟PC外围集成电路
文件页数/大小: 327 页 / 1976 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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DEVICE SPECIFICATION  
S5933  
PCI CONTROLLER  
3.1.4 Arbitration Pins (Bus Masters Only) — PCI Local Bus  
Signal  
REQ#  
GNT#  
Type  
Description  
out  
Request. This signal is sourced by an agent wishing to become the bus master. It is a  
point-to-point signal and each master has its own REQ#.  
in  
Grant. The GNT# signal is a dedicated, point-to-point signal provided to each poten-  
tial bus master and signifies that access to the bus has been granted.  
3.1.5 Error Reporting Pins — PCI Local Bus  
Signal  
Type  
Description  
PERR#  
s/t/s  
Parity Error. This pin is used for reporting parity errors during the data portion of a  
bus transaction for all cycles except a Special Cycle. It is sourced by the agent  
receiving data and driven active two clocks following the detection of the error. This  
signal is driven inactive (high) for one clock cycle prior to returning to the tri-state  
condition.  
SERR#  
o/d  
System Error. This pin is used for reporting address parity errors, data parity errors  
on Special Cycle commands, or any error condition having a catastrophic system  
impact.  
3.1.6 Interrupt Pin — PCI Local Bus  
Signal  
INTA#  
Type  
Description  
o/d  
Interrupt A. This pin is a level sensitive, low active interrupt to the host. The INTA#  
interrupt must be used for any single function device requiring an interrupt capability.  
Applied Micro Circuits Corporation  
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333  
3-6  
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