DEVICE SPECIFICATION
S5933
PCI CONTROLLER
3.1 PCI BUS INTERFACE SIGNALS
3.1.1 Address and Data Pins — PCI Local Bus
Signal
Type
Description
AD[31:00]
t/s
Local Bus Address/Data lines. Address and data are multiplexed on the same pins.
Each bus operation consists of an address phase followed by one or more data
phases. Address phases are identified when the control signal, FRAME#, is asserted.
Data transfers occur during those clock cycles in which control signals IRDY# and
TRDY# are both asserted.
C/BE[3:0]#
t/s
Bus Command and Byte Enables. These are multiplexed on the same pins. During
the address phase of a bus operation, these pins identify the bus command, as
shown in the table below. During the data phase of a bus operation, these pins are
used as Byte Enables, with C/BE[0]# enabling byte 0 (least significant byte) and C/
BE[3]# enabling byte 3 (most significant byte).
C/BE[3:0]#
Description
(during address phase)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Special Cycle
I/O READ
I/O WRITE
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
MEMORY READ - Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
PAR
t/s
Parity. This signal is even parity across the entire AD[31:00] field along with the C/
BE[3:0]# field. The parity is stable in the clock following the address phase and is
sourced by the master. During the data phase for write operations, the bus master
sources this signal on the clock following IRDY# active; during the data phase for
read operations, this signal is sourced by the target and is valid on the clock following
TRDY# active. The PAR signal therefore has the same timing as AD[31:00}, delayed
by one clock.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
3-4
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
