S5933
32-Bit PCI “MatchMaker”
S5933
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32-Bit Master Write Address Register
32-Bit Master Read Address Register
30-Bit Master Read Count Register
28-Bit Master Write Count Register
Figure 5
Summary
Because the PCI bus applies to numerous system architectures, it allows a single add-in card hardware design to be
created for multiple platforms. The PCI standard also provides the bandwidth required for many new, high-perfor-
mance applications.
The AMCC S5933 provides a flexible, low-cost, compliant interface to the PCI bus. The architecture of the S5933
makes it an excellent choice for cards being converted from the ISA/EISA standard, as well as newer applications
requiring high data rates and bus mastering capabilities. These applications include frame grabbers, work station
graphics, satellite receivers, modems, ISDN/FDDI/ATM communications and I/O interfaces. The S5933 allows the
hardware developer to focus on the actual application development rather than debugging the PCI bus interface logic.
This significantly shortens design cycles and decreases development costs.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
6
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
