S5933
32-Bit PCI “MatchMaker”
User
Application
S5933
Pass-Thru Data &
Address Registers
I/O Audio
Bus Master Transfer
Count & Address
Registers
2.1 PCI Local Bus
Interface Logic
ISDN
FDDI
ATM
AMCC
Add-On
Local Bus
Interface Logic
Mux/Demux
Buffers
Graphics/
MPEG/
Grabber
FIFOs
Mux/Demux
Buffers
Mailboxes
Proprietary
Backplane
Read/Write
Control
Configuration
Registers
Satellite
Receiver/
Modem
Status Registers
Serial/Parallel nvRAM
Configuration Space
Expansion BIOS
Figure 1
S5933 Architecture
PCLK
INTA#
RST#
BPCLK
IRQ#
The block diagram in figure 1 above shows the
major functional elements within the S5933. The
S5933 provides three physical bus interfaces: the
PCI Local bus, the user local bus referred to as the
Add-On Local bus and the optional serial and byte-
wide non-volatile memory buses. Data movement
between buses can take place through mailbox reg-
isters or the FIFO data channel, or a user can define
and enable one or more of the four Pass-Thru data
channels. S5933 Bus Master or DMA data transfers
to and from the PCI Local bus are performed
through the FIFO data channel under either Host or
Add-On software control or Add-On hardware con-
trol using dedicated S5933 signal pins.
S5933
Add-On Bus
Control
SYSRST#
Add-On
Data Bus
AD[31:0]
DQ[31:0]
C/BE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
RD#
S5933 Register
Access
REQ#
GNT#
PCI
Local
Bus
FRAME#
DEVSEL#
IRDY#
WR#
PTATN#
PTBURST#
PTNUM[1:0]#
PTBE[3:0]#
PTADR#
TRDY#
IDSEL#
Pass-Thru
Control/Access
STOP#
LOCK#
PTWR
PTRDY#
PAR
The S5933 signal pins are shown in Figure 2 right.
The PCI Local Bus signals are detailed on the left
side; Add-On Local Bus signal are detailed on the
right side. All additional S5933 device control sig-
nals are shown on the lower right side.
PERR#
SERR#
RDFIFO#
WRFIFO#
RDEMPTY
WRFULL
Direct FIFO
Access
MODE
FLT#
SNV
S5933
Control
EA[15:0]
EQ[7:0]
Byte Wide
Config/BIOS Opt.
The S5933 supports a two wire serial nvRAM bus
and a byte-wide EPROM/FLASH bus. This allows
the designer to customize the S5933 configuration
by loading setup information on system power-up.
Serial Bus
Config/BIOS Opt.
EWR#/SDA
ERD#/SCL
Figure 2
S5933 Register Architecture
Control and configuration of the Add-On Local bus, and the MatchMaker itself, is performed through three primary
groups of registers. These groups consist of PCI Configuration Registers, PCI Operation Registers and Add-On Oper-
ation Registers. All these registers are user configurable through their associated bus or from an external non-volatile
memory device. This section will provide a brief overview of each of these register groups and the optional non-vola-
tile interface.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
2
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
