S5933
32-Bit PCI “MatchMaker”
PCI Configuration Registers
All PCI compliant devices are required to pro-
vide a group of Configuration Registers for the
host system. These registers are polled during
power up initialization and contain specific
device and add-in card product information
including Vendor ID, Device ID, Revision and
the amount of memory required for product
operation. The S5933 can either load these reg-
isters with default values or initialize them from
an external non-volatile memory area called
'Configuration Space'. The S5933 can accom-
modate a total of 256 bytes of external memory
for this purpose. The first 64 bytes is reserved
for user defined configuration data which is
loaded into the PCI Configuration Registers
during power-up initialization. The remaining
192 bytes may be used to implement an Expan-
sion BIOS or contain add-in card POST code.
Table 1 shows all the S5933 PCI Configuration
Registers.
Byte 3
Byte 2
Byte 1
Byte 0
Address
Device ID
PCI Status
Vendor ID
00h
PCI Command
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
Class Code
Revision ID
Built-In Self Test
Header Type
Latency Timer
CacheLine Size
Base Address Register 0
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Base Address Register 5
Reserved Space
Reserved Space
Expansion ROM Base Address
Reserved Space
Reserved Space
Max. Latency
Min. Grant
Interrupt Pin
Interrupt Line
PCI Operation Registers
The second group of registers are the PCI Oper-
ation Registers shown in Table 2. This group
consists of sixteen 32-bit (DWORD) registers
Table 1
accessible to the Host processor from the PCI Local bus. These are the main registers through which the PCI Host
configures S5933 operation and communicates with the Add-On Local bus. These registers encompass the PCI bus
incoming and outgoing Mailboxes, FIFO data channel, Bus
Master Address and Count registers, Pass-Thru data channel
registers and S5933 device Status and Control registers.
Address
Offset
PCI Operation Registers
Outgoing Mailbox Register 1 (OMB1)
Outgoing Mailbox Register 2 (OMB2)
Outgoing Mailbox Register 3 (OMB3)
Outgoing Mailbox Register 4 (OMB4)
Incoming Mailbox Register 1 (IMB1)
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
Add-On Bus Operation Registers
The third and last register group consists of the Add-On
Operation Registers, shown in Table 3. This group of eigh-
teen 32-bit (DWORD) registers is accessible to the Add-On
Local bus. These are the main registers through which the
Add-On logic configures S5933 operation and communicates
with the PCI Local bus. These registers encompass the Add-
On bus Mailboxes, Add-On FIFO, DMA Address/Count Reg-
isters (when Add-On initiated Bus Mastering), Pass-Thru
Registers and Status/Control registers.
Incoming Mailbox Register 2 (IMB2)
Incoming Mailbox Register 3 (IMB3)
Incoming Mailbox Register 4 (IMB4)
FIFO Register Port (bidirectional) (FIFO)
Master Write Address Register (MWAR)
Master Write Transfer Count Register (MWTC)
Master Read Address Register (MRAR)
Master Read Transfer Count Register (MRTC)
Mailbox Empty/Full Status Register (MBEF)
Interrupt Control/Status Register (INTCSR)
Bus Master Control/Status Register (MCSR)
Non-Volatile Memory Interface
The S5933 contains a set of PCI Configuration Registers.
These registers can be initialized with default values or with
designer specified values contained in an external nvRAM.
The nvRAM can be either a serial (2 Kbytes, maximum) or a
byte-wide device (64 Kbytes, maximum).
Table 2
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