S5933
32-Bit PCI “MatchMaker”
PTBURST#
PTRDY#
out
in
Pass-Thru Burst. Informs the Add-On bus the current Pass-Thru region decoded PCI bus
cycle is a burst access.
Pass-Thru Ready. This input indicates when Add-On logic has completed a Pass-Thru
cycle and another may be initiated.
PTNUM[1:0]
out
Pass-Thru Number. Identifies which of the four Pass-Thru regions the Host read/write is
requesting. Only valid for the duration of PTATN#. 00 = Base Address Register 1, 01 =
Base Address Register 2, 10 = Base Address Register 3, 11 = Base Address Register 4.
PTBE[3:0]#
PTADR#
out
in
Pass-Thru Byte Enables. During a PCI to Pass-Thru read, Indicates which bytes of a
DWORD is to be written into. During a PCI to Pass-Thru write, indicates which bytes of a
DWORD are valid to read. PTBE[3:0]# are only valid while PTATN# is asserted.
Pass-Thru Address. When asserted, the 32-bit Pass-Thru address register contents is driven
onto the DQ[31:0] bus. All other Add-On control signals must be inactive during the
assertion of PTADR#.
PTWR
SYSRST#
BPCLK
IRQ#
out
out
out
out
in
Pass-Thru Write. This signal indicates the current PCI to Pass-Thru bus transaction is a
read or write cycle. Valid only when PTATN# is active.
System Reset. An active-low buffered PCI bus RST# output signal. The signal is asynchro-
nous and can be asserted through software from the PCI host interface.
Buffered PCI Clock. This output is a buffered form of the PCI bus clock and has all of the
behavioral characteristics of the PCI clock (i.e., DC-to-33 MHz capability).
Interrupt Request. This output signals Add-On logic a significant event has occurred as a
result of activity within the S5933.
FLT#
Float. Floats all S5933 output signals when asserted. This signal is connected to an inter-
nal pull-up resistor.
SNV
in
Serial Non-Volatile Device. This input, when high, indicates that a serial boot device or
that no boot device in present. When this pin is low, a byte-wide boot device is present.
WRFIFO#
in
Write FIFO. This signal provides a method to directly write the FIFO without having to
generate the SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO.
Access width is either 32 bits or 16 bits depending on the data bus size available. This sig-
nal is intended for implementing PCI DMA transfers with the Add-On system. This pin
has an internal pull-up resistor.
RDFIFO#
in
Read FIFO. This signal provides a method to directly read the FIFO without having to
generate the SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO.
Access width is either 32 bits or 16 bits depending on the data bus size defined by the
MODE pin. This signal is intended for implementing PCI DMA transfers with the Add-On
system. This pin has an internal pull-up resistor.
WRFULL
out
out
Write FIFO Full. This pin indicates whether the Add-On-to-PCI bus FIFO is able to
accept more data. This pin is intended to be used to implement DMA hardware on the
Add-On system bus. A logic low output from this pin can be used to represent a DMA
write (Add-On-to-PCI FIFO) request.
RDEMTPY
Read FIFO Empty. This pin indicates whether the read FIFO (PCI-to-Add-On FIFO) con-
tains data. This pin is intended to be used by the Add-On system to control DMA transfers
from the PCI bus to the ADd-On system bus. A logic low from this pin can be used to rep-
resent a DMA (PCI-to-Add-On FIFO) request.
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