Revision 1.02 – April 12, 2007
S5920 – PCI Product: Pass-Thru Operation
Data Book
address into the Pass-Thru Address Register (APTA).
If the S5920 determines that the address is within one
of its defined Pass-Thru regions, it indicates to the
Add-On that a write to the Pass-Thru Data Register or
Pass-Thru Read FIFO (APTD) is required.
Figure 68. PCI to Add-On Passive Burst Read
3
4
7
8
9
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
0h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
WR#
D1
D2
D3
D4
Fh
2Ch
0h
DQ[31:0]
PTADR#
PTRDY#
ADDR
Data 1 Data 2
Data 3
Data 4
Figure 9 shows a Passive Mode Pass-Thru burst read
access (Add-On write) of four DWORDs, using
PTADR# to provide an address-phase.
PTNUM[1:0] 1h. Indicates the access is to Pass-Thru
region 1.
PTWR Deasserted. Indicates the access is a read.
Clock 0: PCI address information is stored in the
Pass-Thru Address Register. The address is recog-
nized as a PCI read of Pass-Thru region 1. Add-On
bus signals PTATN#, PTBURST#, PTNUM[1:0],
PTWR and PTBE[3:0] will update on the next rising
edge of ADCLK
PTBE[3:0]# D1. Indicates valid bytes for the first data
transfer.
Clock 2: The Add-On logic has sampled PTATN# and
PTBURST# active, indicating that at least two read
data transfers are requested by the PCI. The Add-On
will start servicing the Burst Read transfer by first read-
ing the Pass-Thru Address via the PTADR# input. This
is an asynchronous read, meaning that the address
will appear on DQ after a propagation delay from the
assertion of PTADR#. In the event that the address is
not required, this cycle and the next could be skipped
(as the next clock provides a turn-around cycle).
Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
PTATN# Asserted. Indicates Pass-Thru access is
pending.
Clock 3: The Add-On logic will latch the Pass-Thru
address on the rising edge of this clock. This cycle is
also required to avoid contention on the DQ bus. Time
must be allowed after PTADR# is deasserted for the
PTBURST# Asserted. The access has multiple data
phases.
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