Revision 1.02 – April 12, 2007
S5920 – PCI Product: PCI Bus Protocol
Data Book
Table 52. PCI Bus Commands (Continued)
C/BE[3:0]#
Command Type
Supported
No
1101
Reserved
1110
1111
Memory Read Line
Yes 1
Memory Write and Invalidate
Yes 2
1. Memory Read Multiple and Memory Read Line are executed as a Memory Read.
2. Memory Write and Invalidate is executed as a Memory Write.
cates that the next access needs to be a completely
new cycle.
PCI BURST TRANSFERS
The PCI bus, by default, expects burst transfers to be
executed. To successfully perform a burst transfer,
both the initiator and target must order their burst
address sequence in an identical fashion. There are
two different ordering schemes: linear address incre-
menting and 80486 cache line fill sequencing.
Some accesses to the S5920 controller do not support
burst transfers. For example, the S5920 does not
allow burst transfers when accesses are made to the
configuration or operation registers. Attempts to per-
form burst transfers to these regions will cause a
disconnect on the PCI bus, as described above.
Expansion ROM accesses also do not support bursts,
and will respond in the same way. Accesses to mem-
ory or I/O regions defined by the Base Address
Registers 1-4 may be bursts, if desired.
The S5920 supports only linear burst ordering.
Attempts to perform burst transfers with a scheme
other than this will cause the STOP# signal to be
asserted during the first data phase, thus issuing a dis-
connect to the initiator. The S5920 completes the initial
data phase successfully, but asserting STOP# indi-
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