Revision 1.02 – April 12, 2007
S5920 – PCI Product: Initialization
Data Book
Figure 44. Type 0 Configuration Write Cycles
EXPANSION BIOS ROMS
0
12345
This section provides an example of a typical PC-com-
patible expansion BIOS ROM. Address offsets 040h
through 07Fh represent the portion of the external nv
memory used to boot-load the S5920 controller.
PCI CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
Whether the expansion ROM is intended to be execut-
able code is determined by the contents of the first
three locations (starting at offset 0h) and a byte check-
sum over the defined length. The defined length is
specified in the byte at address offset 0002h. Table 2
lists each field location by its address offset, its length,
its value, and description.
DATA
ADD
1011
BYTE EN
TRDY#
IDSEL
The following represents the boot-load image for the
S5920 controller’s PCI configuration register:
DEVSEL#
Table 50. PC Compatible Expansion ROM
Byte Offset
0h
Byte Length (decimal)
Binary Value
55h
Description
BIOS ROM signature byte 1
BIOS ROM signature byte 2
Length in multiples of 512 bytes
Entry point for INIT function.
Reserved (application unique data)
Pointer to PCI Data Structure
user-defined
Example
55h
1
1
1h
AAh
AAh
2h
1
variable
variable
variable
variable
variable
Vendor ID
Device ID
not used
01h
3h
4
7h-17h
18h-19h
1Ah-3Fh
40h
17
2
38
2
(see page 2-23)
10E8h
5920h
xxh
42h
2
(see page 2-24)
44h
1
45h
1
S5920 Special
Modes
01h
(see page 2-89 and 2-129)
46h
48h
49h
4Ch
4Dh
4Eh
2
1
3
1
1
1
not used
Revision ID
class code
not used
xxxxh
00h
(see page 2-29)
(see page 2-30)
FF0000h
xxh
not used
xxh
your header
type
00h
(see page 2-37)
(see page 2-38)
4Fh
1
self-test, if
desired
80h or 00h
AMCC Confidential and Proprietary
DS1596
99
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
