Revision 1.02 – April 12, 2007
S5920 – PCI Product: PCI Bus Protocol
Data Book
Target Latency
Figure 50. Figure 5. Target-Initiated Retry
The PCI specification requires that a selected target
relinquish the bus should an access to that target
require more than eight PCI clock periods (16 clocks
for the first data phase, 8 clocks for each subsequent
data phase). This prevents slow target devices from
potentially monopolizing the PCI bus and also allows
more accurate estimations for bus access latency.
1
2
3
4
5
PCLK
(I)
FRAME#
IRDY#
TRDY#
(I)
(T)
Note that a special mode is available to the user which
will allow for this mechanism to be disabled, thus vio-
lating the PCI 2.1 Specification. If a value of 0 is
programmed into the serial nvRAM location 45h, bit 0,
target latency is ignored. In this case, the S5920 will
never issue a retry/disconnect in the event of a slow
Add-On device. This programmable bit is only pro-
vided for flexibility, and most users should leave this bit
set to 1.
DEVSEL# (T)
(T)
STOP#
Initiator
Sequences IRDY#
+ FRAME# to return
to IDLE state
(I) Driven by Initiator
(T) Driven by Target
Target Retry
Signaled
nvRAM Location 45h, bit 0 = 0 : No disconnect for slow
Add-On device.
Figure 51. Figure 6. Engaging the LOCK# Signal
1
2
3
4
5
nvRAM Location 45h, bit 0 = 1 : PCI 2.1 compliant
PCLK
Target Locking
(I)
FRAME#
LOCK#
AD[31:0]
It is possible for a PCI bus master to obtain exclusive
access to a target (“locking”) through use of the PCI
bus signal LOCK#. LOCK# is different from the other
PCI bus signals because its ownership may belong to
any bus master, even if it does not currently have own-
ership of the PCI bus. The ownership of LOCK#, if not
already claimed by another master, may be achieved
by the current PCI bus master on the clock period fol-
lowing the initial assertion of FRAME#. Figure 6
describes the signal relationship for establishing a
lock. The ownership of LOCK#, once established, per-
sists even while other bus masters control the bus.
Ownership can only be relinquished by the master
which originally established the lock.
(T
(I)
(I)
)
Address
Data
IRDY#
(T)
TRDY#
DEVSEL#
(T)
LOCK
MECHANISM
AVAILABLE
UPON FIRST
ACCESS
TARGET
BECOMES
LOCKED
(I) Driven by Initiator
(T) Driven by Target
BUS
IDLE
LOCK MECHANISM
AVAILABLE
LOCK
ESTABLISHED
PCI Bus Access Latency Components
LOCK
MAINTAINED
Bus Access Latency
TRDY#
Asserted
GNT#
Asserted
FRAME#
Asserted
REQ#
Asserted
--Arbitration Latency-- --Bus Acquisition-- --Target Latency--
Latency
AMCC Confidential and Proprietary
DS1596
106
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
