Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
PCI Write Transfers
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•
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The memory target aborts the transfer
PCI bus grant (GNT# is removed)
Write transfers on the PCI bus are one clock period
shorter than read transfers. This is because the
AD[31:0] bus does not require a turn-around cycle
between the address and data phases. When the
S5335 is accessed (target), it responds to a PCI bus
memory or I/O transfers. As a PCI initiator, the S5335
controller can also execute PCI memory write
operations.
The Add-On to PCI FIFO becomes empty
A higher priority (PCI to Add-On) S5335 trans-
fer is pending (if programmed for priority)
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•
The write transfer byte count reaches zero
Bus mastering is disabled from the Add-On
interface
Write accesses to the S5335 operation registers
(S5335 as a target) are shown in Figure 50. Here, the
S5335 asserts the signal STOP# in clock period 3.
STOP# is asserted because the S5335 supports fast,
zero-wait-state write cycles but does not support burst
writes to operation registers. Wait states may be
added by the initiator by not asserting the signal
IRDY# during clock 2 and beyond. There is only one
condition where writes to S5335 operation registers do
not return TRDY# (but do assert STOP#). This is
called a target-initiated termination or target discon-
nect and occurs when a write attempt is made to a full
S5335 FIFO. As with the read transfers, the assertion
of STOP# without the assertion of TRDY# indicates
the initiator should retry the operation later.
The timing diagram in Figure 49 represents an S5335
initiator PCI write operation transferring to a fast, zero-
wait-state memory target. The signals driven by the
S5335 during the transfer are FRAME#, AD[31:0], C/
BE[3:0]#, and IRDY#. The signals driven by the target
are DEVSEL# and TRDY#. As with PCI reads, targets
assert DEVSEL# and TRDY# after the clock defining
the end of the address phase (boundary of clock peri-
ods 1 and 2 of Figure 49). TRDY# is not driven until
the target has accepted the data for the PCI write.
When the S5335 becomes the PCI initiator, it attempts
sustained zero-wait state burst writes until one of the
following occurs:
Figure 49. Zero Wait State Burst Write PCI Bus Transfer (S5335 as Initiator)
2
3
4
6
1
5
PCICLOCK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
(I)
ADDRESS
DATA 1
DATA 2
DATA 3
(I)
BUS COMMAND*
BYTE EN 1
BYTE EN 2
BYTE EN 3
(I)
(I)
TRDY#
(T)
(T)
DEVSEL#
(I) = DRIVEN BY INITIATOR
(T) = DRIVENBY TARGET
DATA
TRANSFER
#1
DATA
TRANSFER
DATA
TRANSFER
#3
* BUSCOMMAND = MEMORYWRITE
#2
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
