Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Initiator Preemption
Latency Timer register can cause two preemption
situations:
A PCI initiator (bus master) is said to be preempted
when the system platform deasserts the initiator’s bus
grant signal, GNT#, while it still requests the bus
(REQ# asserted). This situation occurs if the initiator’s
latency timer expires and the system platform (bus
arbitrator) has a bus master request from another
device. The S5335 Master Latency Timer register con-
trols the S5335 responsiveness to the removal of a
bus grant (preemption). The presence of a Master
1. Removal of GNT# when the latency timer is non-
zero (S5335 is guaranteed to still “own the bus”).
2. Removal of the GNT# after the latency timer has
expired.
The first situation is depicted in Figure 52, when the
latency timer has not expired. Preemption with a zero
or expired latency timer is shown in Figure 53.
Figure 52. Master Initiated Termination Due to Preemption and Latency Timer Active (S5335 as Master)
3
6
1
2
4
5
PCI CLOCK
GNT #
FRAME
IRDY#
(I)
(I)
TRDY#
(T)
S5335
LATENCY
TIMER
=1
=0
=3
=2
(I) = DRIVEN BY INITIATOR
(T) = DRIVENBY TARGET
PREEMPTION
DATA
TIMEOUT
SENSED
DATA
TRANSFERRED
DATA
DATA
TRANSFERRED
TRANSFERRED
TRANSFERRED
Figure 53. Master Initiated Termination Due to Preemption and Latency Timer Expired (S5335 as Master)
3
1
2
4
5
PCICLOCK
GNT#
(I)
FRAME
IRDY# (I)
TRDY# (T)
S5335
LATENCY
TIMER
=1
=0
(I) =DRIVEN BY INITIATOR
(T)= DRIVEN BY TARGET
DATA
TRANSFERRED
PREEMPTION
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