Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Master-Initiated Termination
Normal Cycle Completion
Occasionally, a PCI transfer must be terminated by the
initiator. Typically, the initiator terminates a transfer
upon the successful completion of the transfer. Some-
times, the initiator’s bus mastership is relinquished by
the bus arbiter (GNT# is removed), often because
another device requires bus ownership. This is called
initiator preemption and is discussed in later Sections.
When the S5335 is an initiator and does not observe a
DEVSEL# response to its assertion of FRAME#, it ter-
minates the cycle (master abort).
A successful data transfer occurs when both the initia-
tor and target assert their respective ready signals,
IRDY# and TRDY#. The last data phase is indicated
by the initiator when FRAME# is deasserted during a
data transfer. A normal cycle completion occurred if
the target does not assert STOP#. Figure 51 shows
the signal relationships defining a normal transfer
completion.
Figure 50. Single Data Phase PCI Bus Write of S5335 Registers (S5335 as Target)
2
3
4
5
6
1
PCI CLOCK
FRAME
AD[31:0]
#
(I)
IF BURST
ATTEMPT
DATA 1
ADDRESS
DATA 2
(I)
C/BE[3:0]#
IRDY#
BYTE EN 1
BYTE EN 2
BUSCOMMAND
(I)
(I)
TRDY#
(T)
(T)
(T)
DEVSEL#
STOP#
NO
(I) = DRIVEN BY INITIATOR
(T) = DRIVENBY TARGET
DATA
TRANSFER #1
DATA
TRANSFERRED
Figure 51. Master-Initiated, Normal Completion (S5335 as either Target or Initiator)
3
2
1
PCI CLOCK
FRAME #
IRDY#
(I)
(I)
TRDY#
(T)
(T)
(T)
DEVSEL#
STOP#
NORMAL
COMPLETION
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
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