Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Table 39. Read Response (Memory Assigned) to an All-Ones Write Operation to a Base Address Register
Response
00000000h
Size in bytes
[EPROM boot value]1
00000000h or BIOS missing2,3
FFFFFFF0h
FFFFFFE0h
FFFFFFC0h
FFFFFF80h
FFFFFF00h
FFFFFE00h
FFFFFC00h
FFFFF800h
FFFFF000h
FFFFE000h
FFFFC000h
FFFF8000h
FFFF0000h
FFFE0000h
FFFC0000h
FFF80000h
FFF00000h
FFE00000h
FFC00000h
FF800000h
FF000000h
FE000000h
FC000000h
F8000000h
none - disabled
FFFFFFF0h
FFFFFFE0h
FFFFFFC0h
FFFFFF80h
FFFFFF00h
FFFFFE00h
FFFFFC00h
FFFFF800h
FFFFF000h
FFFFE000h
FFFFC000h
FFFF8000h
FFFF0000h
FFFE0000h
FFFC0000h
FFF80000h
FFF00000h
FFE00000h
FFC00000h
FF800000h
FF000000h
FE000000h
FC000000h
F8000000h
F0000000h
E0000000h
16 bytes (4 DWORDs)
32 bytes (8 DWORDs)
64 bytes (16 DWORDs)
128 bytes (32 DWORDs)
256 bytes (64 DWORDs)
512 bytes (128 DWORDs)
1K bytes (256 DWORDs)
2K bytes (512 DWORDs)
4K bytes (1K DWORDs)
8K bytes (2K DWORDs)
16K bytes (4K DWORDs)
32K bytes (8K DWORDs)
64K bytes (16K DWORDs)
128K bytes (32K DWORDs)
256K bytes (64K DWORDs)
512K bytes (128K DWORDs)
1M bytes (256K DWORDs)
2M bytes (512K DWORDs)
4M bytes (1M DWORDs)
8M bytes (2M DWORDs)
16M bytes (4M DWORDs)
32M bytes (8M DWORDs)
64M bytes (16M DWORDs)
128M bytes (32M DWORDs)
256M bytes (64M DWORDs)
512M bytes (128M DWORDs)
F0000000h
E0000000h
1. The two most significant bits define bus width for BADR1:4 in Pass-Thru operation).
2. Bits D3, D2 and D1 may be set to indicate other attributes for the memory space. See text for details.
3. BADR5 register is not implemented and will return all 0’s.
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