Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Base Address Registers (BADR)
Determining Base Address Size
The address space defined by a given base address
register is determined by writing all 1s to a given base
address register from the PCI bus and then reading
that register back. The number of 0s returned starting
from D4 for memory space and D2 for I/O space
toward the high-order bits reveals the amount of
address space desired. Tables 39 and 40 list the pos-
sible returned values and their corresponding size for
both memory and I/O, respectively. Included in the
table are the nvRAM/EPROM boot values which corre-
spond to a given assigned size. A register returning all
zeros is disabled.
Base Address
Register Name:
Address Offset:
Power-up value:
10h, 14h, 18h, 1Ch, 20h, 24h
FFFFFFC1h for offset 10h;
00000000h for all others
External nvRAM offset 050h, 54h,
58h, 5Ch, 60h (BADR0-4)
Boot-load:
Attribute:
Size:
high bits Read/Write; low bits Read
Only
32 bits
Assigning the Base Address
After a base address has been sized as described in
the preceding paragraph, the region associated with
that base address register (the high order one bits)
can physically locate it in memory (or I/O) space. For
example, if the first base address register returns
FFFFFFC1h indicating an I/O space (D0=1) and is
then written with the value 00000300h. This means
that the controller’s internal registers can be selected
for I/O addresses between 00000300h through
0000033Fh, in this example. The base address value
must be on a natural binary boundary for the required
size (example 300h, 340h, 380h etc.; 338h would not
be allowable).
The base address registers provide a mechanism for
assigning memory or I/O space for the Add-On func-
tion. The actual location(s) the Add-On function is to
respond to is determined by first interrogating these
registers to ascertain the size or space desired, and
then writing the high-order field of each register to
place it physically in the system’s address space. Bit
zero of each field is used to select whether the space
required is to be decoded as memory (bit 0 = 0) or I/O
(bit 0 = 1). Since this PCI controller has 16 DWORDs
of internal operating registers, the Base Address Reg-
ister at offset 10h is assigned to them. The remaining
five base address registers can only be used by boot-
loading them from the external nvRAM interface.
BADR5 register is not implemented and will return all
0’s.
AMCC Confidential and Proprietary
DS1657 44
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
