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S5335QFAAB 参数 Datasheet PDF下载

S5335QFAAB图片预览
型号: S5335QFAAB
PDF下载: 下载PDF文件 查看货源
内容描述: PCI总线控制器, 3.3V [PCI Bus Controller, 3.3V]
分类和应用: 总线控制器PC
文件页数/大小: 189 页 / 2175 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 5.01 – November 30, 2005  
S5335 – PCI Bus Controller, 3.3V  
Data Sheet  
Expansion ROM Base Address Register (XROM)  
The expansion base address ROM register provides a  
mechanism for assigning a space within physical  
memory for an expansion ROM. Access from the PCI  
bus to the memory space defined by this register will  
cause one or more accesses to the S5335 controllers’  
external BIOS ROM (or nvRAM) interface. Since PCI  
bus accesses to the ROM may be 32 bits wide,  
repeated operations to the ROM are generated by the  
S5335 and the wider data is assembled internal to the  
S5335 controller and then transferred to the PCI bus  
by the S5335.  
Expansion ROM Base Address  
30h  
Register Name:  
Address Offset:  
Power-up value:  
Boot-load:  
00000000h  
External nvRAM offset 70h  
bits 31:11, bit 0 Read/Write; bits 10:1  
Read Only  
Attribute:  
32 bits  
Size:  
Figure 19. Expansion ROM Base Address Register  
31  
11 10  
1
0
0
Bit  
0
Value  
Address Decode  
Enable (RW)  
0=Disabled  
1=Enabled  
Reserved (RO)  
Programmable (R/W)  
Table 41. Expansion ROM Base Address Register  
Bit  
Description  
31:11 Expansion ROM Base Address Location. These bits are used to position the decoded region in memory space. Only  
bits which return a 1 after being written as 1 are usable for this purpose. These bits are individually enabled by the  
contents sourced from the external boot memory (EPROM or nvRAM). The desired size for the ROM memory is  
determined by writing all ones to this register and then reading back the contents. The number of bits returned as  
zeros, in order from least significant to most significant bit, indicates the size of the expansion ROM. This controller  
limits the expansion ROM area to 64K bytes. The allowable returned values after all ones are written to this register  
are shown in TTable 42.  
10:1  
0
Reserved. All zeros.  
Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit. When this bit is  
set, the decoder is enabled; when this bit is zero, the decoder is disabled. It is required that the PCI command regis-  
ter also have the memory decode enabled for this bit to have an effect.  
AMCC Confidential and Proprietary  
DS1657 49