Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
the FIFO condition after it advances, and are updated
off of the rising edge of BPCLK. When RDFIFO# is
deasserted, the DQ bus floats. The next time
RDFIFO# is asserted, data 2 is presented on the DQ
bus (as there was no BPCLK edge to advance the
FIFO).
ten (or an empty FIFO is read) by a PCI initiator, the
S5335 requests a retry. The faster the Add-On inter-
face can empty (or fill) the FIFO, the less often retries
occur. With the S5335 as a PCI initiator, a similar situ-
ation occurs. Not emptying or filling the FIFO quickly
enough results in the S5335 giving up control of the
PCI bus. Higher PCI bus data transfer rates are possi-
ble through the FIFO with a synchronous interface.
A synchronous FIFO interface has the advantage of
allowing data to be accessed more quickly (in bursts)
by the Add-On. As a target, if a full S5335 FIFO is writ-
Figure 81. Synchronous FIFO Register Burst Read Access Example
FIFO Pointer Advances
BPCLK
BE[3:0]#
ADR[6:2]
DQ[31:0]
Valid Byte Enables
Valid Address
Data 0
Data 1
Data 2
SELECT#
RD#
Status Before Read
New Status
New Status
RDEMPTY
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